An analog to digital converter (ADC) is a device which converts an analog input signal into an accurate binary number (represented by the status of one or more output bits) proportional to the amplitude of the analog signal. Numerous methods exist for performing the analog to digital conversion. A full "flash" ADC is the fastest method and utilizes a set of comparators operating in parallel, each comparing the analog input signal to a different reference voltage. If the amplitude of the analog input signal is greater than the reference level, the output of the comparator will be in a high logic state; conversely, if the amplitude of the analog input signal is less than the reference level, the output of the comparator will be in a low logic state. The output of each comparator is latched and the signals at all of the outputs are sent simultaneously to a decoder, the output of which is the desired digital representation of the analog input at a particular point in time.
In order to obtain a digital output having N bits, it is necessary to provide (2.sup.N -1) comparators, latches and reference voltage levels. The reference levels are generally established through the use of precision resistors connected in series. The tap between two adjacent resistors is connected to one input of a comparator and the other input of the comparator receives the analog input signal
The digital output of the comparators is in the form of a "thermometer code": when the output of a comparator P is in a high logic state, the outputs of all of the comparators "below" comparator P (coupled to reference voltages less than the reference voltage coupled to comparator P) are also in the high logic state. In a like manner, if the output of a comparator P + 1 is in a low logic state, then the outputs of all comparators above P + 1 (coupled to reference voltages greater than the reference voltage coupled to comparator P + 1) are also in a low logic state. Thus, even though the only significant information is contained at the point of transition between a comparator which is on and the comparator above it which is off, many more comparators may be in a high logic state and an equal number of latches will be latched leading to unnecessary use of circuit elements and power. Furthermore, as previously noted, a decoder is necessary to convert the thermometer code output of the comparators into useful binary information. Consequently, despite its high speed parallel operation, a flash ADC may become prohibitively expensive in terms of cost, number of parts (comparators, latches, decoder and resistor string), power consumed and space required when resolution greater than about 8 bits is required.
An alternative which requires fewer parts than a full flash converter is a sub-ranging ADC. The sub-ranger utilizes two or more smaller flash converters (one for the most significant bits (MSB) and one for the least significant bits (LSB)) and a digital to analog converter (DAC). The analog input signal is sent to the coarse flash converter which produces the most significant bits in the manner described above. The digital output from the coarse converter is converted back into an analog value by the DAC whose output is subtracted from the original analog input signal. The resulting analog difference signal is then sent to the fine flash converter where the least significant bits are produced.
By way of comparison, an 8-bit full flash converter would require (2.sup.8 -1), or 255, comparators and an equal number of latches. An 8-bit sub-ranger having four most significant bits produced by the coarse converter and four least significant bits produced by the fine converter would require (2.sup.4 -1), or 15, comparators and latches in each of the two converter sections for a total of 30 comparators and 30 latches. A disadvantage of the sub-ranger is that obtaining the most significant bits from the coarse converter and then converting these back into an analog signal in the DAC entails a certain amount of time. A sample-and-hold circuit is generally required at the input of the converter to hold the input signal during the analog-to-digital-to-analog operation. At certain frequencies, the slower speed of a sub-ranger, caused by the delay in the interim conversion back to analog, may be unacceptable. Furthermore, like the full flash converter, the sub-ranger requires a decoder in order to obtain useful binary information.
An analog to digital conversion technique which does not require the use of a decoder is successive approximation. In contrast to flash and sub-ranging converters, the successive approximation converter generates each bit of the output sequentially, beginning with the most significant bit, and the output can be read directly without the use of a decoder or separate coarse and fine converters. A successive approximation register (SAR) controls the operation of the converter by generating inputs to a DAC. The output of the DAC is compared to the analog input signal in a comparator whose output is coupled to the register.
The output of a SAR may be read directly without the need for a decoder while one comparator and N latches are needed for an N bit converter.
An ADC which combines the high speed performance of a full flash converter with the size and cost advantages of a sub-ranger is a folding ADC. By "folding" the changing analog input signal into two or more sections, the number of latches can be reduced significantly. For example, if the analog input signal is an increasing ramp, the output from the folding circuit is, ideally, a repetitive triangular wave-form having a frequency of K times the frequency of the input ramp, where K is the number of times the full scale input range is divided or folded into equal sections. The output is then processed by a fine converter to obtain the least significant bits. A coarse flash converter generates the most significant bits of the ADC.
Like a full flash ADC, no separate DAC is required since the folding function incorporates the DAC function. The speed of a folding ADC can compare very favorably with that of a full flash converter if care is taken to match delays between analog input and clock signals. Like a sub-ranger, fewer comparators and latches are required; thus, the cost and space requirements of a folding ADC compare favorably with those of a sub-ranger.
Nonetheless, a folding ADC has certain disadvantages which the full flash and sub-ranger do not have. The folding circuit includes differential pairs whose outputs are non-linear for large signal excursions. A resulting disadvantage is that at the upper and lower ends of the input range, the non-linearities may occur due to incomplete switching of certain of the differential pairs in the folding circuit. The problem of such non-linearities has not been addressed in known ADC circuits.
Because of the non-ideal nature of the differential pairs, the output of the folding circuit tends to resemble a rounded triangular wave or a sinusoid rather than a perfect triangular wave. At the extreme values of the sinusoid (peak and trough) the output of the folding circuit may be nearly constant even though the input is changing. This rounding off of the ideal triangular waveform results in lower resolution of the folding circuit output
One method for reducing the errors caused by rounding at the peaks and troughs of the folding circuit output is the use of two folding circuits or "sides", whose inputs connect to alternate reference ladder taps and whose outputs are offset from each other in voltage phase (for example, by 90.degree.), together with additional circuitry which selects one or the other side depending on which is in a linear range. Thus, before the output of the first folding side leaves its linear range, the output of the second folding side enters its linear range and is selected for processing by the fine converter.
To generate L least significant bits, 2.sup.L folding signals are necessary. To reduce the number of folding circuits without decreasing the resolution, or to increase the resolution without increasing the number of folding circuits, an interpolation network can be used. With this technique, additional signals can be derived between the outputs of the existing folding circuits. For example, to obtain four least significant bits from a fine flash converter, sixteen (2.sup.4) folding signals are required. These may be generated from sixteen folding circuits or, alternatively, eight signals may be generated from eight folding circuits with the remaining eight signals derived by a two times interpolation network between the eight outputs of the folding circuits. This results in a 50% reduction in the number of folding circuits and associated circuit elements.
As previously noted, the differential pairs in comparators do not switch instantly between high and low outputs. Instead, the output tends to follow the input over a certain range which includes the point at which the comparator would ideally change states (the zero crossing point where the two comparator inputs are equal). To obtain an interpolated signal halfway between two folding outputs, the outputs of known interpolation circuits are coupled to a resistive divider network from which three signals, the two original signals plus one interpolated signal from a center tap between two resistors, can be obtained.
A significant disadvantage in relying upon a resistive network to generate the interpolated signals is the requirement that the resistors be extremely precise. Also, time delays between various input signal paths may not match. The spread time delays causes aperture skews that become "jitter" errors at high frequencies. The resistive network may also take up valuable space on an integrated circuit and may generate heat which must be dissipated away from the circuit.
Consequently, a need has arisen for a high resolution analog to digital converter capable of high speed/high frequency operation having a reasonable size and cost without the time delay errors and non-linearities common to existing folding circuitry.